1. Field of the Invention
The present invention generally relates to an active control circuit of a Pseudo Static Random Access Memory (hereinafter, referred to as “PSRAM”), and more specifically, to a technology of enabling a normal operation even when a page address toggles at any timing in a page operation.
2. Description of the Related Art
In general, a Dynamic Random Access Memory (hereinafter, referred to as “DRAM”) memorizes information as a type of charges in a capacitor, shares the charges in a corresponding bit line through a transistor, and amplify the shared charges in a sense amplifier to read data.
The above-described DRAM which comprises a transistor and a capacitor embodies a memory having a large memory capacity with a small area.
Meanwhile, elements of a memory device become miniaturized for the purpose of high-speed operation of memory devices, reduction of current consumption and miniaturization of processing systems.
As a result of miniaturization of devices, the area of the memory cell capacitor becomes smaller, so that the capacity of the memory cell capacitor is reduced.
If the value of the capacity of the memory cell capacitor becomes smaller, the amount of retained charges is reduced even when the same voltage level of data is written in the capacitor.
In order to compensate the decrease in the amount of retained charges, a refresh operation is periodically performed. Here, the refresh operation is amplified by a sense amplifier after the data stored in the memory cell capacitor is read in a bit line, and then the amplified data is rewritten in the original memory cell capacitor.
When a data retaining characteristic is degraded in a miniaturized device, a refresh cycle is required to be short in order to compensate the degradation of the data retaining characteristic. However, when the refresh cycle becomes short, an external processing device is inaccessible to the DRAM, so that the performance of the processing system is degraded.
Additionally, when the refresh cycle becomes short, current consumption for the refresh operation is increased. Specifically, the short refresh cycle does not satisfy a low standby current condition required in a data retaining mode of a portable battery driving device that requires low current consumption.
In order to solve the problem of the refresh operation in the DRAM, a PSRAM has been known which is a DRAM operated like a SRAM (Static Random Access Memory).
In the PSRAM, a cycle for performing read/write operations on common data and a refresh cycle for performing a refresh operation on data are successively performed for one cycle in a memory access cycle. Since the refresh operation is performed in one access cycle, the refresh operation can be hidden on the external access to operate a DRAM as a SRAM.
In a row path of a general memory device, a row address is inputted to select a word line corresponding to a row address from a plurality of word lines. Then, data stored in a memory cell connected to the selected word line are transmitted by charge sharing to a bit line, and a bit line sense amplifier senses a micro-data signal on a bit line to amplify the signal to a level having a full swing width.
In a column path of a memory device, a column address is inputted to select a memory cell corresponding to a column address from a plurality of memory cells connected to a specific word line selected by a row address, thereby outputting data on a bit line to the outside.
Generally, it takes more time in the row path than in the column path because the row path is longer than the column path.
A page mode has been introduced to perform the more effective read or write operation in the memory device. Here, a page means a memory cell that shares the same word line and has a different column address.
As a result, both of a row path and a column path are not performed whenever data are stored or read in a memory cell. A row path is once performed at an initial stage, and only a column path is changed by changing a column address while a word line is activated, so that a read/write operation is operated at a high speed.
FIG. 1 is a block diagram illustrating a page access control circuit of a conventional PSRAM.
The conventional page access control circuit comprises an address buffer 2, a page address detecting unit 4, a column control unit 6 and a column selecting unit 8.
The address buffer 2 receives a page address ADD<0:2> from an external address pin, and detects an address transition timing in response to an address strobe signal add_stb to generate a page address transition detecting signal ATDB21 0:2>.
The page address detecting unit 4 generates a page address detecting signal atdsumb_page which detects when a page address toggles in response to the address transition detecting signal ATDB<0:2>.
The column control unit 6 receives the page address detecting signal atdsumb_page to generate a write/read operation strobe signal wtdr_stb.
The column selecting unit 8 generates a column selecting signal Yi in response to the write/read operation strobe signal wtdr_stb.
FIG. 2 is a timing diagram illustrating the operation of the page access control circuit of the conventional PSRAM of FIG. 1. Here, FIG. 2 shows a simulation diagram when the column selecting signal Yi is double enabled (A).
In the PSRAM whose page operation is performed asynchronously, a normal address ADD<20> for enabling a word line WL toggles first, and then a page address ADD<0> toggles after a time of tRC (generally, 70˜85 ns).
If the normal address ADDM<20> for enabling the word line WL toggles and the page address ADD<0> toggles before the tRC so that the page address ADD<0> meats a high level period of the write/read operation strobe signal wtdr_stb, the column selecting signal Yi is double enabled like the period A of FIG. 2.
In other words, if the normal address ADD<20> for enabling the word line WL toggles and the page address ADD<0> toggles before tRC, the toggle of the page address ADD<0> is regarded as an error. As a result, the toggle is ignored or two or more page addresses are accessed, so that two or more columns are selected to destroy data or cause mis-operations.